1. Technical Field
The present invention relates generally to a deskew apparatus and method for Peripheral Component Interconnect (PCI) Express and, more particularly, to a deskew apparatus and method for PCI Express which align input data in PCI Express on an 18-bit basis, thereby compensating for static skew as well as dynamic skew.
2. Description of the Related Art
The speed of PCI Express was typically 2.5 Gbps in its early stage, and is now 5 Gbps in line with the trend of favoring high speed. An 8-Gbp device is expected to be released in the near future. The unit of data that is basically used in PCI Express is 1 byte, that is, 8 bits. In the early 2.5 Gbp scheme, the data width and operating speed of an interface in a serial/parallel device were 8 bits and 250 MHz or 16 bits and 125 MHz. In the recent 5 Gbp scheme, however, the data width and operating speed of the interface are typically 16 bits and 250 MHz because of the limitations of a protocol engine. In the case of 8 Gbps, there is the strong possibility of the data width and operating speed of the interface being 16 bits and 500 MHz or 32 bits and 250 MHz.
Accordingly, when received data is 16-bit data or 32-bit data, bytes forming the data are not aligned, and thus there is a need for a logic for additionally aligning the packets of a physical layer, a data link layer and a transaction layer when detecting the packets.
In this PCI Express standard, when a multi-channel skew occurs, it is recommended that a multi-channel skew be performed using a COM symbol inside a TS sequence set or an SKP sequence set, that is, physical layer packets. The use of other deskew devices is optional.
FIG. 1 is a diagram schematically showing the structure of a conventional deskew apparatus based on 9-bit data input. Referring to FIG. 1, the conventional deskew apparatus aligns data based on 1 byte, that is, 8 bits (i.e., the basic unit of the PCI Express standard), +1 bit=9 bits and only a COM symbol. In this deskew apparatus, a reference lane processor 20 receives 9-bit data from the 9-bit data input unit 10 of a reference lane, and the received 9-bit data is stored in the 9-bit register 21 of the reference lane processor 20 in accordance with a clock. Data is transmitted to lower 9-bit registers 22 to 26 per clock cycle. A COM comparator 27 is attached to the 9-bit register 26, that is, a final stage, and generates a value of 1 whenever a COM symbol is generated. The value of the 9-bit register 26, that is, the final stage, becomes the output value of the reference lane processor 20 and is output to a 9-bit data output unit 70. An additional lane processor 40 receives 9-bit data from a 9-bit data input unit 30, that is, an additional lane, and the received 9-bit data is stored in the 9-bit register 41 of the additional lane processor 40 in accordance with a clock. Data is propagated to lower 9-bit registers 41 to 51 per clock cycle. COM comparators 52 to 62 are attached to the respective 9-bit registers 41 to 51, and each generates a value of 1 whenever a COM symbol is generated. Here, an 11×9 bit data selector 63 determines which of the COM comparators 52 to 62 has a value of 1 when the output value of each of the COM comparators 52 to 62 becomes 1. Then the 11×9 bit data selector 63 determines the value that is selected from among the values of the 9-bit registers 41 to 51 based on the results of the determination. The value selected by the 11×9 bit data selector 63 is output to a 9-bit data output unit 80.
The conventional deskew apparatus configured to have the above-described configuration and align data based only on a COM symbol is disclosed in Korean Unexamined Patent Publication No. 2006-0081522 (published on Jul. 13, 2006) entitled “Method of Compensating for Byte Skew of PCI Express and PCI Express Physical Layer Receiver for the Same.” The conventional deskew apparatus is not problematic when data including transmission information comes immediately after a COM symbol because data is aligned such that data after the COM symbol has the same timing. However, it is problematic in that a byte skew is not compensated for when an SKP symbol is transmitted after a COM symbol and the SKP symbol is added or deleted.
Accordingly, there is an urgent need for a method and apparatus for appropriately compensating for a skew regardless of the addition or deletion of an SKP symbol in PCI Express.